Intermediate IoT Development · Intermediate
Embedded C for IoT: Interrupt Discipline
Structure ISR-safe code paths with traceable state machines.
Overview
Refactor blocking loops into staged tasks, document volatile semantics, and capture timing diagrams mentors annotate line-by-line.
Included focus areas
- ISR sizing worksheets
- Volatile usage audits
- State machine diagrams with guard clauses
- Unit harness stubs without hardware
- Timing capture with logic analyzer screenshots
- Code review checklist for nested interrupts
- Memory pool exercises with leak guards
Outcomes you can evidence
- Pass mentor ISR audit without critical findings
- Ship annotated timing diagrams for three modules
- Maintain test doubles runnable in CI stub mode
FAQ
RTOS?
Introduced conceptually; labs stay bare-metal focused.
Compiler?
GCC-arm none-eabi supported; others via office hours only.
Certificate?
Certificate of completion; external certs not included.
Participant notes
“Volatile audit caught two races our CI missed. Wish the RTOS teaser went deeper—still solid.”